# Synthesis & Static Timing Analysis (STA) Engineer at Voltai

Synthesis & Static Timing Analysis (STA) Engineer at Voltai in Palo Alto Office. Full-time. Posted October 19, 2026.

- Company: Voltai
- Location: Palo Alto Office
- Job type: Full-time
- Experience: 5+ years
- Posted: 2026-10-19
- Apply: https://jobs.ashbyhq.com/voltai.careers/7c63cbec-6567-4e75-a953-a6f1668ff70b/application
- Source: https://jobmagic.ai/jobs/synthesis-static-timing-analysis-sta-engineer-voltai-13yb6h

## Requirements

- 5+ years of synthesis and STA experience on production tapeouts.
- Deep experience with Design Compiler/Fusion Compiler or Genus, and PrimeTime or Tempus.
- Strong SDC skills: clocks, exceptions, generated clocks, and multi-mode constraints.
- Experience with logic equivalence checking (Formality or Conformal).
- Strong Tcl and Python scripting.

## Description

**About Voltai**
Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.
**About the Team**
Backed by Silicon Valley’s top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), the inventors of IC3 and the Murphi verification system, CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents.
**About this Role**
You'll own the path from RTL to a timing-clean netlist. You'll close timing on real silicon programs with leading semiconductor companies while helping Voltai's AI learn to write constraints, diagnose violations, and close timing.
**What You’ll Do**

- Own logic synthesis and constraint development (SDC) for blocks and full chips.

- Drive timing closure across corners and modes, working with RTL and physical design teams.

- Run and sign off STA, including on-chip variation, crosstalk, and multi-corner multi-mode analysis.

- Perform logic equivalence checking between RTL and netlist.

- Build automation that makes synthesis and timing flows faster and more reliable.

- Evaluate AI-generated constraints and timing fixes, and help define what good looks like.

**What We’re Looking For**

- 5+ years of synthesis and STA experience on production tapeouts.

- Deep experience with Design Compiler/Fusion Compiler or Genus, and PrimeTime or Tempus.

- Strong SDC skills: clocks, exceptions, generated clocks, and multi-mode constraints.

- Experience with logic equivalence checking (Formality or Conformal).

- Strong Tcl and Python scripting.

**Bonus Points**

- Advanced node experience (7nm and below).

- Experience with ECO flows and timing signoff methodology.

- Interest in AI-assisted design tools.