# RTL Design Engineer at Voltai

RTL Design Engineer at Voltai in Palo Alto Office. Full-time. Posted October 19, 2026.

- Company: Voltai
- Location: Palo Alto Office
- Job type: Full-time
- Experience: 5+ years
- Posted: 2026-10-19
- Apply: https://jobs.ashbyhq.com/voltai.careers/cfcbeff3-2cf0-4a20-ba2a-12706d44eb6f/application
- Source: https://jobmagic.ai/jobs/rtl-design-engineer-voltai-afdt93

## Requirements

- 5+ years of RTL design experience on chips that taped out.
- Expert SystemVerilog/Verilog and strong microarchitecture skills.
- Hands-on experience with lint, CDC, synthesis, and timing-aware design.
- Familiarity with common protocols (AXI, PCIe, Ethernet, DDR, or similar).
- Python or Tcl scripting.

## Description

**About Voltai**
Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.
**About the Team**
Backed by Silicon Valley’s top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), the inventors of IC3 and the Murphi verification system, CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents.
**About this Role**
You'll design and own RTL for production silicon, from microarchitecture to signoff-ready code. You'll work on real chip programs with leading semiconductor companies while helping Voltai's AI learn to write, review, and debug RTL the way the best designers do.
**What You’ll Do**

- Own microarchitecture and RTL implementation for IP blocks and subsystems in SystemVerilog.

- Drive designs through lint, CDC/RDC, synthesis, and timing closure with the backend team.

- Partner with verification and formal teams on test plans, assertions, and coverage closure.

- Debug complex functional and timing issues across simulation, emulation, and silicon.

- Review and evaluate AI-generated RTL, and help define what correct, high-quality design looks like.

- Work directly with customer design teams when needed.

**What We’re Looking For**

- 5+ years of RTL design experience on chips that taped out.

- Expert SystemVerilog/Verilog and strong microarchitecture skills.

- Hands-on experience with lint, CDC, synthesis, and timing-aware design.

- Familiarity with common protocols (AXI, PCIe, Ethernet, DDR, or similar).

- Python or Tcl scripting.

**Bonus Points**

- Experience writing SVA or working with formal verification.

- Low-power design (UPF, clock and power gating).

- Interest in AI-assisted design tools.