# Physical Design Engineer at Voltai

Physical Design Engineer at Voltai in Palo Alto Office. Full-time. Posted October 19, 2026.

- Company: Voltai
- Location: Palo Alto Office
- Job type: Full-time
- Experience: 5+ years
- Posted: 2026-10-19
- Apply: https://jobs.ashbyhq.com/voltai.careers/58731161-17e4-47ad-a67b-98899a35e782/application
- Source: https://jobmagic.ai/jobs/physical-design-engineer-voltai-kw64hv

## Requirements

- 5+ years of physical design experience with multiple production tapeouts.
- Deep experience with Innovus or Fusion Compiler/ICC2.
- Strong understanding of timing closure, clock tree synthesis, and power distribution networks.
- Experience at advanced nodes (7nm and below).
- Strong Tcl and Python scripting.

## Description

**About Voltai**
Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.
**About the Team**
Backed by Silicon Valley’s top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), the inventors of IC3 and the Murphi verification system, CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents.
**About this Role**
You'll take designs from netlist to GDSII. You'll own floorplanning through closure on real silicon programs with leading semiconductor companies while helping Voltai's AI learn how expert physical designers make decisions.
**What You’ll Do**

- Own block-level and full-chip physical implementation: floorplanning, placement, clock tree synthesis, and routing.

- Drive timing, power, and congestion closure with synthesis and STA teams.

- Close physical verification (DRC/LVS) and power integrity (IR drop, EM) for signoff.

- Build and improve place-and-route flows and automation.

- Evaluate AI-generated floorplans and implementation decisions, and help define what good looks like.

- Work directly with customer teams on implementation challenges.

**What We’re Looking For**

- 5+ years of physical design experience with multiple production tapeouts.

- Deep experience with Innovus or Fusion Compiler/ICC2.

- Strong understanding of timing closure, clock tree synthesis, and power distribution networks.

- Experience at advanced nodes (7nm and below).

- Strong Tcl and Python scripting.

**Bonus Points**

- Full-chip integration or hierarchical design experience.

- Experience with high-speed or low-power designs.

- Interest in AI or machine learning applied to physical design.